Cell-Aware Test
Cell-Aware Test
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细胞感知测试
DOI:
10.1109/tcad.2014.2323216
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发表时间:
2014
影响因子:
2.9
通讯作者:
A. Fast
中科院分区:
文献类型:
--
作者:
F. Hapke;W. Redemund;Andreas Glowatz;J. Rajski;Michael Reese;M. Hustava;Martin Keim;J. Schlöffel;A. Fast
This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generation for 1,940 standard library cells, as well as the application of CAT to several industrial designs. We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million. We also present CAT diagnosis and physical failure analysis results from one failing part and give an outlook for using the functionality for quickly ramping up the yield in advanced technology nodes.