A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2
A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2
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DOI：
10.1109/jssc.2009.2032723
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发表时间：
2009-12-01
影响因子：
5.4
通讯作者：
Nauta, Bram
中科院分区：
文献类型：
--
作者：
Gao, Xiang;Klumperink, Eric A. M.;Nauta, Bram
本文提出了一种基于2.2GHz低抖动欠采样的锁相环。它使用相位检测器/电荷泵（PD/CP），利用参考时钟对VCO输出进行二次采样。与经典PLL中发生的情况相反，在该子采样PLL中，PD/CP噪声不乘以N-2，从而导致来自PD/CP的低噪声贡献。此外，在锁定状态下不需要分频器，因此可以消除分频器噪声和功率。添加的频率锁定环可确保正确的频率锁定，而不会降低锁定时的抖动性能。PLL采用标准的0.18 μ m CMOS工艺实现。该器件采用1.8 V电源供电，功耗为4.2 mA，有效面积为0.4 x 0.45 mm（2）。分频比为40时，200 kHz偏移处的带内相位噪声测量值为-126 dBc/Hz。在10 kHz至40 MHz范围内积分的均方根PLL输出抖动为0.15 ps。
This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N-2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18-mu m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 x 0.45 mm(2). With a frequency division ratio of 40, the in-band phase noise at 200 kHz offset is measured to be -126 dBc/Hz. The rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps.