Measurement of a clock-tuned digital non-Foster circuit for positive or negative digital capacitance
Measurement of a clock-tuned digital non-Foster circuit for positive or negative digital capacitance
复制标题
测量时钟调谐数字非福斯特电路的正或负数字电容
DOI：
10.1109/secon.2017.7925354
复制
发表时间：
2017
期刊：
影响因子：
--
通讯作者：
T. Weldon
中科院分区：
文献类型：
--
作者：
P. Kehoe;Killian K. Steer;T. Weldon
理论和测量结果提出了一个时钟调谐数字电容，提供一个可变的非福斯特负电容或可变的正电容的数字实现。与以前的数字非福斯特电容器设计不同，所提出的方法提供可变电容，而无需更改信号处理硬件或嵌入式软件。相反，单个外部时钟提供了对电路可变负或正电容的简单控制。理论结果表明，预测数字电容与时钟频率成反比，相关的寄生电阻由设计参数决定。仿真结果和样机测量验证了该方法的有效性。
Theory and measured results are presented for a clock-tuned digital capacitor that provides digital implementation of a variable non-Foster negative capacitance or a variable positive capacitance. Unlike previous digital non-Foster capacitor designs, the proposed approach provides a variable capacitance without requiring changes to the signal processing hardware or embedded software. Instead, a single external clock provides simple control of the variable negative or positive capacitance of the circuit. Theoretical results are provided showing that predicted digital capacitance is inversely proportional to clock frequency, and associated parasitic resistance is determined by design parameters. Simulation results and prototype measurements confirm the underlying theory, and demonstrate the efficacy of the proposed approach.