Impact of NO Annealing on Flatband Voltage Instability due to Charge Trapping in SiС MOS Devices
Impact of NO Annealing on Flatband Voltage Instability due to Charge Trapping in SiС MOS Devices
复制标题
NO 退火对 SiС MOS 器件中电荷俘获引起的平带电压不稳定性的影响
DOI:
10.4028/www.scientific.net/msf.858.599
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发表时间:
2016
期刊:
影响因子:
--
通讯作者:
Heiji Watanabe
中科院分区:
文献类型:
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作者:
Yoshihito Katsu;T. Hosoi;Y. Nanen;T. Kimoto;T. Shimura;Heiji Watanabe
We evaluated the effect of NO annealing on hole trapping characteristic of SiC metal-oxide-semiconductor (MOS) capacitor by measuring flatband voltage (VFB) shifts during a constant negative gate voltage stress under UV illumination. Under low stress voltages, the VFB shift due to hole trapping was found to be suppressed by NO annealing. However, the VFB shift of the NO-annealed device increases significantly with stress time under high stress voltage conditions, while the device without NO annealing showed only a slight shift. This result implies that NO annealing enhances generation of hole traps, leading to the degradation of SiC-MOS devices in long-term reliability.