Weighted p-Bits for FPGA Implementation of Probabilistic Circuits
Weighted p-Bits for FPGA Implementation of Probabilistic Circuits
复制标题
DOI：
10.1109/tnnls.2018.2874565
复制
发表时间：
2019-06-01
影响因子：
10.4
通讯作者：
Camsari, Kerem Y.
中科院分区：
文献类型：
--
作者：
Pervaiz, Ahmed Zeeshan;Sutton, Brian M.;Camsari, Kerem Y.
概率自旋逻辑是最近提出的一种基于称为概率比特(p比特)的不稳定随机单元的计算范例，这些比特可以被关联以形成概率电路(p电路)。这些p-电路可以用来解决优化、推理的问题，并实现精确的布尔函数，在这种模式下，给定的布尔电路可以反向操作，以找到与给定输出一致的输入组合。在本文中，我们提出了一种可扩展的现场可编程门阵列实现这种可逆P-电路。我们实现了一个将随机单元与本地化存储结构相结合的“加权”p位。我们还给出了一个加权p比特的广义瓦片，它可以映射到可逆布尔逻辑之外的一大类问题上，以及如何通过在硬件上解决这个问题的一个小实例来将可逆性应用于有趣的问题，如NP-完全子集和问题。
Probabilistic spin logic is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits (p-bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve the problems of optimization, inference, and implement precise Boolean functions in an "inverted" mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this brief, we present a scalable field-programmable gate array implementation of such invertible p-circuits. We implement a "weighted" p-bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted p-bits to which a large class of problems beyond invertible Boolean logic can be mapped and how invertibility can be applied to interesting problems such as the NP-cmplete subset sum problem by solving a small instance of this problem in hardware.