Transistor-level based defect tolerance for reliable nanoelectronics
Transistor-level based defect tolerance for reliable nanoelectronics
复制标题
基于晶体管级的缺陷容限，实现可靠的纳米电子学
DOI：
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发表时间：
2008
期刊：
影响因子：
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通讯作者：
A. Melouki
中科院分区：
文献类型：
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作者：
A. El;B. Al;A. Melouki
基于纳米器件的电路设计将基于接受设计中高百分比的器件将是有缺陷的。在这项工作中，我们调查的缺陷容忍技术，增加了冗余的晶体管级，并提供内置的免疫力永久性缺陷（stuck-open，stuck-short和桥梁）。所提出的技术是基于四晶体管结构，保证所有的单一缺陷和大量的多个缺陷的理论分析和仿真验证的缺陷容限取代每个晶体管。如使用ISCAS 85和89基准电路的广泛模拟结果所示，所研究的技术实现了比最近报道的纳米电子缺陷容限技术（即使晶体管缺陷概率高达4至5倍）显着更高的缺陷容限，并减少面积开销。
Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by quadded-transistor structure that guarantees defect tolerance of all single defects and a large number of multiple defects as validated by theoretical analysis and simulation. As demonstrated by extensive simulation results using ISCAS 85 and 89 benchmark circuits, the investigated technique achieves significantly higher defect tolerance than recently reported nanoelectronics defect-tolerant techniques (even with up to 4 to 5 times more transistor defect probability) and at reduced area overhead.