Impacts of high-k gate dielectrics and low temperature on the performance of nanoscale CNTFETs
Impacts of high-k gate dielectrics and low temperature on the performance of nanoscale CNTFETs
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高 k 栅极电介质和低温对纳米级 CNTFET 性能的影响
DOI：
10.1007/s10825-016-0901-7
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发表时间：
2016
影响因子：
2.1
通讯作者：
F. Djeffal
中科院分区：
文献类型：
--
作者：
Rechem Djamil;Khial Aicha;Azizi Cherifa;F. Djeffal
通过数值模拟模型研究了栅介质材料对碳纳米管场效应晶体管性能的影响。该模型基于二维非平衡格林函数形式，通过泊松和薛定谔方程的自洽解来执行。从漏电流、通态电流、电流比、亚阈值斜率、漏极感应势垒降低以及跨导、漏极电导和本征栅极延迟方面研究了器件性能。这项研究是在从室温到 100 K 的低温介电常数范围内进行的。
The influence of gate dielectric materials on the performance of a carbon nanotube field-effect transistor has been studied by a numerical simulation model. This model is based on a two-dimensional nonequilibrium Green’s function formalism performed with the self-consistent solution of the Poisson and Schrödinger equations. The device performance is investigated in terms of leakage current, on-state current,current ratio, subthreshold slope, drain-induced barrier lowering, as well as transconductance, drain conductance, and intrinsic gate delay. This study is carried out over a wide range of dielectric permittivities at low temperatures ranging from room temperature down to 100 K.