X-compact: an efficient response compaction technique
X-compact: an efficient response compaction technique
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DOI：
10.1109/tcad.2004.823341
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发表时间：
2004-03
影响因子：
2.9
通讯作者：
S. Mitra;Kee-sup Kim
中科院分区：
文献类型：
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作者：
S. Mitra;Kee-sup Kim
X-Compact是一种耐X耐受的测试反应压实技术。它可以使测试响应数据量的指数减少以及从芯片中收集测试响应所需的引脚数量。压实硬件需要可忽略不计的区域，在正常操作过程中不会增加任何额外的延迟，即使在存在未知逻辑值（通常称为X）的情况下，也可以保证发现有缺陷的芯片，并为大多数实际情况保留诊断功能。该技术对当前的设计和测试流有最小的影响，可用于减少测试时间，测试数据量，测试输入/输出引脚和测试人员通道，并提高测试质量。
X-Compact is an X-tolerant test response compaction technique. It enables up to exponential reduction in the test response data volume and the number of pins required to collect test response from a chip. The compaction hardware requires negligible area, does not add any extra delay during normal operation, guarantees detection of defective chips even in the presence of unknown logic values (often referred to as X's), and preserves diagnosis capabilities for most practical scenarios. The technique has minimum impact on current design and test flows, and can be used to reduce test time, test-data volume, test-input/output pins and tester channels, and also to improve test quality.