A 5.25-GHz CMOS folded-cascode even-harmonic mixer for low-voltage applications
A 5.25-GHz CMOS folded-cascode even-harmonic mixer for low-voltage applications
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DOI：
10.1109/tmtt.2005.862665
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发表时间：
2006-02
影响因子：
4.3
通讯作者：
Ming-Feng Huang;C. Kuo;Shuenn-Yuh Lee
中科院分区：
文献类型：
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作者：
Ming-Feng Huang;C. Kuo;Shuenn-Yuh Lee
本文提出了一种用于低压应用的5.25 GHz折叠共源共栅偶次谐波混频器（FEHM）。该FEHM采用折叠技术来降低裕量电压，在RF级中采用电流复用电路来提高其线性度，并且在本振（LO）级中采用倍频技术来产生LO倍频信号。此外，所提出的技术具有高转换增益的优点。为了证明的好处和优化电路设计，转换增益，线性度和噪声性能的理论研究进行了说明。在0.9V电源电压和5.5dBm本振功率下，FEHM的转换增益为8.3dB，三阶输入交调截点（IIP/sub 3/）为0.03dBm，二阶输入交调截点（IIP/sub 2/）为31.2dBm。在中频500 kHz时，该混频器的功耗约为4.95 mW。
This paper presents a 5.25-GHz folded-cascode even-harmonic mixer (FEHM) for low-voltage applications. This FEHM employs the folded technique to reduce the headroom voltage, a current reuse circuit in the RF stage to improve its linearity, and the frequency-doubling technique in the local oscillator (LO) stage to produce an LO double-frequency signal. In addition, the proposed technique exhibits the advantage of high conversion gain. In order to demonstrate the benefits and optimize the circuit design, the theoretical studies of conversion gain, linearity, and noise performance are described. For measurement, the proposed FEHM possesses conversion gain of 8.3 dB, third-order input intercept point (IIP/sub 3/) of 0.03 dBm, and second-order input intercept point (IIP/sub 2/) of 31.2 dBm under the supply voltage of 0.9 V and LO power of 5.5 dBm. The power consumption of the proposed mixer is about 4.95 mW at an IF frequency of 500 kHz.