Self-Healing Circuits Using Statistical Element Selection
Self-Healing Circuits Using Statistical Element Selection
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使用统计元件选择的自愈电路
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
Gokce Keskin
中科院分区：
文献类型：
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作者：
Gokce Keskin
由于集成电路技术的不断扩展，设计人员面临着创建鲁棒的模拟和混合信号电路设计的挑战。在先进的CMOS节点中，小特征尺寸的随机管芯内变化的增加严重限制了模拟/混合信号电路的缩放益处，电压余量逐渐减小。本章详细介绍了统计元素选择（SES）的方法，依赖于子集数量的组合增长。利用可选择的电路元件，随机性可用于提供制造后配置以实现规范。校准方法证明了两个硅的结果在65 nm CMOS工艺。一个测试芯片包括一个数字校准比较器阵列，具有内置的组合冗余。超过99.5%的比较器械达到了给定的偏心距要求，而Peldom型尺寸的这一比例为15%。另一个测试芯片是8位、1.5GS/s闪存ADC。在1.3GHz的ERBW下，样机的SNDR为37 dB，功耗为35 mW，优值为0.42pJ/conv-step。
Due to the ongoing aggressive scaling of integrated circuit technologies, designers are challenged by creating robust analog and mixed-signal circuit designs. The increasing random intra-die variations of small feature sizes in advanced CMOS nodes severely limit the benefits of scaling for analog/mixed-signal circuits with the diminishing voltage headroom. This chapter describes the details of the statistical element selection (SES) methodology that relies on the combinatorial growth in number of subsets. With selectable circuit elements, the randomness can be used to provide post-manufacturing configuration to achieve specifications. The calibration methodology is demonstrated with two silicon results in 65nm CMOS technology. One test chip consists of an array of digitally calibrated comparators with built-in combinatorial redundancy. Over 99.5% of the comparators reach the given offset requirement compared to 15% for Pelgrom-type sizing. The other test chip is an 8-bit, 1.5GS/s flash ADC. The prototype achieves 37dB of SNDR with 1.3GHz ERBW for 35mW power consumption and 0.42pJ/conv-step of figure of merit.