Copper line topology impact on the SiOCH low-k reliability in sub 45nm technology node. From the time-dependent dielectric breakdown to the product lifetime
Copper line topology impact on the SiOCH low-k reliability in sub 45nm technology node. From the time-dependent dielectric breakdown to the product lifetime
复制标题
铜线拓扑对 45nm 以下技术节点中 SiOCH 低 k 可靠性的影响。
DOI：
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
J. Chaix
中科院分区：
文献类型：
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作者：
M. Vilmay;D. Roy;C. Monget;F. Volpi;J. Chaix
Sioch Low-k介电材料在铜互连中的引入与45 nm以下技术节点的关键尺寸缩减相关，这对可靠性工程师来说是一个挑战。与低k电介质击穿有关的电路损耗现在正成为一个主要问题。随着线距的减小，对铜线拓扑结构的控制逐渐成为控制低k电介质可靠性的一阶参数。要提高Low-k可靠性，需要区分各种拓扑效应，并在产品层面上量化其对寿命的影响。本文论证了铜线形状、线边缘粗糙度(LER)和晶片内中线间距变化对Low-k介质可靠性的重要性。此外，描述了简单的分析模型来量化每一种对时间相关介质击穿(TDDB)的影响，特别是对最终产品寿命的影响。给出了避免错误寿命预测的几点建议。
SiOCH low-k dielectrics introduction in copper interconnects associated to the critical dimensions reduction in sub 45nm technology nodes is a challenge for reliability engineers. Circuit wear-out linked to low-k dielectric breakdown is now becoming a major concern. With the reduction of the line to line spacing, the control of the copper line topology is becoming a first order parameter governing the low-k dielectric reliability. Improving the low-k reliability requires to discriminate each topological effect and quantify its impact on the lifetime at product level. This paper demonstrates the importance of the copper line shape, of the line edge roughness (LER) and of the median line to line spacing variation within the wafer on the low-k dielectrics reliability. Moreover, simple analytical models are described to quantify each effect on the Time-Dependant Dielectric Breakdown (TDDB) and particularly on the final product lifetime. Some advices are given to avoid erroneous lifetime projection.