A 14-bit current-mode /spl Sigma//spl Delta/ DAC based upon rotated data weighted averaging
A 14-bit current-mode /spl Sigma//spl Delta/ DAC based upon rotated data weighted averaging
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DOI：
10.1109/4.859496
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发表时间：
2000-08
影响因子：
5.4
通讯作者：
Russell E. Radke;A. Eshraghi;T. Fiez
中科院分区：
文献类型：
--
作者：
Russell E. Radke;A. Eshraghi;T. Fiez
在/SPL倍/过采样、转换带宽为25 kHz的三阶/SPL Sigma//SPL Delta/数模转换器中实现了一种新的动态元素匹配算法--旋转数据加权平均算法。在14位转换器的设计中考虑了系统误差和随机误差。/SPL Sigma//SPL Delta/DAC采用2/SPL mU/m CMOS工艺制造，并包括片上重构滤波器。原型的设计是为了测试DAC在没有DEM、有数据加权平均(DWA)和有RDWA的情况下的性能。结果表明，新的RDWA算法能够实现一阶噪声整形，同时消除了DWA算法中存在的与信号相关的谐波失真。
A new dynamic element matching (DEM) algorithm, referred to as rotated data weighted averaging (RDWA), is implemented in a third-order /spl Sigma//spl Delta/ digital-to-analog converter (DAC) with 64/spl times/ oversampling and a conversion bandwidth of 25 kHz. The systematic and random errors are considered in the design of the 14-bit converter. The /spl Sigma//spl Delta/ DAC is fabricated in a 2-/spl mu/m CMOS process and includes the on-chip reconstruction filter. The prototype was designed to test the performance of the DAC without DEM, with data weighted averaging (DWA), and with RDWA. The results show that the new RDWA algorithm is capable of achieving first-order noise shaping while eliminating the signal-dependent harmonic distortion present in DWA.