Guarded evaluation: pushing power management to logic synthesis/design
Guarded evaluation: pushing power management to logic synthesis/design
复制标题
保护评估：将电源管理推向逻辑综合/设计
DOI：
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发表时间：
1995
期刊：
影响因子：
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通讯作者：
P. Ashar
中科院分区：
文献类型：
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作者：
V. Tiwari;S. Malik;P. Ashar
系统设计的各个层面都清楚地认识到降低下一代数字系统功耗的必要性。在系统级别，电源管理是一项非常强大的技术，可以带来大量且明确的节省。电源管理背后的思想可以扩展到逻辑层。这将涉及确定电路的哪些部分正在计算将被使用的结果，哪些不被使用。然后，不需要的部分就会被“关闭”。本文描述了一种称为保护评估的方法，它是这一想法的实现。提出了构成该方法基础的理论框架和算法。基本思想是自动确定可以在每个时钟周期禁用的电路部分。这节省了电路这些部分中所有无用转换所使用的功率。初步实验表明，这种方法可以节省大量电能，并且对于大量基准电路具有强大的潜力。虽然本文介绍了这些思想在设计逻辑级别的发展，但相同的思想也可以直接应用于设计的寄存器传输级别。
The need to reduce the power consumption of the next generation of digital systems is clearly recognized at all levels of system design. At the system level, power management is a very powerful technique and delivers large and unambiguous savings. The ideas behind power management can be extended to the logic level. This would involve determining which parts of a circuit are computing results that will be used and which are not. The parts that are not needed are then "shut off." This paper describes an approach termed guarded evaluation, which is an implementation of this idea. A theoretical framework and the algorithms that form the basis of the approach are presented. The underlying idea is to automatically determine the parts of the circuit that can be disabled on a per-clock-cycle basis. This saves the power used in all the useless transitions in those parts of the circuit. Initial experiments indicate substantial power savings and the strong potential of this approach for a large number of benchmark circuits. While this paper presents the development of these ideas at the logic level of design, the same ideas have direct application at the register-transfer level of design also.