Inductance of superconductor integrated circuit features with sizes down to 120 nm
Inductance of superconductor integrated circuit features with sizes down to 120 nm
复制标题
超导集成电路的电感特性尺寸小至120 nm
DOI：
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发表时间：
2021
期刊：
影响因子：
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通讯作者：
V. Bolkhovsky
中科院分区：
文献类型：
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作者：
S. K. Tolpygo;E. Golden;T. Weir;V. Bolkhovsky
提供了超导数字集成电路中使用的各种特征的电感数据：线宽低至120 nm的微带和带状线电感器以及接地平面层的不同组合、接地平面中各种尺寸的穿孔及其到电感器的距离对电感的影响、相邻层之间各种尺寸的过孔的电感、远距离超导层之间的复合过孔的电感。用于测量的测试电路是在麻省理工学院林肯实验室为超导电子器件开发的具有八个铌层的完全平坦化工艺的新 150 nm 节点以及最小特征尺寸为 250 nm 的标准 SFQ5ee 和 SC1 制造工艺中制造的。新的 SC2 工艺利用 193 nm 光刻技术，结合等离子体蚀刻和层间电介质的化学机械平坦化，在关键层上定义线宽低至约 100 nm 的电感器。标准工艺使用 248 nm 光刻技术。将测量数据与使用软件包 InductEx 和 wxLC 提取电感的结果进行比较。讨论了由制造工艺引起的电路电感器的变化。讨论了地平面护城河中的磁通量捕获及其与附近电感器的耦合，以用于几种配置的残余磁场中的电路冷却。
Data are presented on the inductance of various features used in superconductor digital integrated circuits: microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers, inductance of composite vias between distant superconducting layers. Test circuits used for the measurements were fabricated in a new 150 nm node of a fully planarized process with eight niobium layers developed at MIT Lincoln Laboratory for superconductor electronics as well as in our standard SFQ5ee and SC1 fabrication processes with 250 nm minimum feature size. The new SC2 process utilizes 193 nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. The standard processes use 248 nm photolithography. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Variations of circuit inductors caused by the fabrication processes are discussed. Magnetic flux trapping in ground plane moats and its coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations.