Achieving 550 MHz in an ASIC methodology
Achieving 550 MHz in an ASIC methodology
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通过 ASIC 方法实现 550 MHz
DOI：
10.1145/378239.378542
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发表时间：
2001
期刊：
影响因子：
--
通讯作者：
K. Keutzer
中科院分区：
文献类型：
--
作者：
D. Chinnery;B. Nikolić;K. Keutzer
通常，好的自动化ASIC设计可能比手工制作的定制设计慢两到五倍。在去年的DAC上，对此进行了检查，并确定了定制电路和ASIC之间速度差距的原因。特别是，更快的定制速度是由以下因素组合实现的：具有良好平衡流水线的良好架构；紧凑的逻辑设计；最大限度地减少时序开销；仔细的布局规划、分区和布局；动态逻辑；布局后晶体管和布线尺寸；以及芯片的快速装仓。缩小速度差距需要尽可能改善ASIC中的这些相同因素。在这篇文章中，我们研究了一个实际例子，说明如何在ASIC中改进这些因素。特别是，我们展示了如何在ASIC设计流程中应用定制设计中常见的技术来设计高速550 MHz磁盘驱动器读取通道。
Typically, good automated ASIC designs may be two to five times slower than handcrafted custom designs. At last year's DAC this was examined and causes of the speed gap between custom circuits and ASICs were identified. In particular, faster custom speeds are achieved by a combination of factors: good architecture with well-balanced pipelines; compact logic design; timing overhead minimization; careful floorplanning, partitioning and placement; dynamic logic; post-layout transistor and wire sizing; and speed binning of chips. Closing the speed gap requires improving these same factors in ASICs, as far as possible. In this paper we examine a practical example of how these factors may be improved in ASICs. In particular we show how techniques commonly found in custom design were applied to design a high-speed 550 MHz disk drive read channel in an ASIC design flow.