Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization
Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization
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DOI：
10.1109/tvlsi.2018.2812893
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发表时间：
2018-03
影响因子：
2.8
通讯作者：
Hayate Okuhara;Akram Ben Ahmed;Johannes Maximilian Kühn;H. Amano
中科院分区：
文献类型：
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作者：
Hayate Okuhara;Akram Ben Ahmed;Johannes Maximilian Kühn;H. Amano
体偏置控制是广泛用于在超低功耗系统中提供泄漏功率和性能之间的有效折衷的基本技术。因此，大量的研究，电源优化，提供最佳的电源和体偏置电压已经进行。然而，考虑到实际的电压源，常规方法遭受有限的性能/功率控制粒度，并且可能导致能量效率方面的降级。因此，本文提出了一种提高性能/功率控制粒度的功率优化方法，并使用真实的处理器芯片进行了评估。在所提出的优化中，nMOSFET和pMOSFET的体偏置被独立控制，而传统的方法统一控制它们。这增加了可能的电压组合的数量，并且允许更精细的目标频率选择，从而以优化复杂性为代价，比传统方法产生更低的功耗。为了减轻这种复杂性，所提出的优化是基于简单的功率和延迟模型。基于模型的优化不需要在真实的芯片测试阶段进行蛮力搜索，因此可以显著减少测试时间和成本。由于模型的系数是用真实的切屑测量值来提取的，所以模型的误差平均可以被抑制到百分之几。所提出的方法进行了验证，真实的芯片实现了65纳米全耗尽绝缘体上硅技术。评估结果表明，所提出的优化是一个有效的手段，降低功耗的泄漏电流占主导地位的芯片。事实上，与传统方法相比，所提出的方法实现了9.617%的平均功耗降低，在V850微控制器的情况下达到22.77%。
Body bias control is a fundamental technique widely used to provide an efficient tradeoff between leakage power and performance in ultralow-power systems. Therefore, a lot of research about power optimization which provides optimal power supply and body bias voltages has been carried out. However, considering the actual voltage sources, the conventional approaches suffer from limited performance/power control granularity and may lead to degradation in terms of the energy efficiency. Therefore, in this paper, a power optimization method that improves the performance/power control granularity is proposed and evaluated with real processor chips. In the proposed optimization, the body biases for nMOSFET and pMOSFET are controlled independently, while the conventional methods control them uniformly. This increases the number of possible voltage combinations and allows finer target frequency selection leading to lower power consumption than the conventional methods at the cost of the optimization complexity. In order to ease this complexity, the proposed optimization is based on simple power and delay models. The model-based optimization does not require brute force search in the phase of real chip testing; thus, the testing time and cost can be significantly reduced. Since the coefficients of the models are extracted with real chip measurements, the error of the model can be suppressed to a few percent in average. The proposed approach is validated by real chips implemented with a 65-nm fully depleted silicon on insulator technology. The evaluation results show that the proposed optimization is an efficient mean of power reduction for a leakage current dominant chip. In fact, when compared with the conventional method, the proposed approach achieves 9.617% of average power reduction reaching up to 22.77% in the case of the V850 microcontroller.