RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAs
RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAs
复制标题
RoRA：基于 SRAM 的 FPGA 的面向可靠性的布局布线算法
DOI：
--
复制
发表时间：
2005
期刊：
影响因子：
--
通讯作者：
M. Violante
中科院分区：
文献类型：
--
作者：
L. Sterpone;M. Reorda;M. Violante
基于SRAM的FPGA设计极易受到单粒子翻转（SEU）的影响。由于配置存储器定义了基于SRAM的现场可编程门阵列（FPGA）实现的电路，因此由配置存储器中的SEU引起的任何变化都可能彻底修改所实现的电路。当这些设备用于安全关键应用时，需要能够减轻FPGA配置存储器中SEU的影响的容错技术。在本文中，我们提出了一个面向可靠性的地方和路线的算法，能够减轻所考虑的颠覆的影响。
SRAM-based FPGA designs are extremely susceptible to single event upset (SEUs). Since the configuration memory defines which is the circuit an SRAM-based field programmable gate array (FPGA) implements, any change induced by SEUs in the configuration memory may modify drastically the implemented circuit. When such devices are used in safety-critical applications, fault tolerant techniques are needed able to mitigate the effects of SEUs in FPGA's configuration memory. In this paper we present a reliability-oriented place and route algorithm that is able to mitigate the effects of the considered upsets.