3D module placement for congestion and power noise reduction
3D module placement for congestion and power noise reduction
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DOI：
10.1145/1057661.1057770
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发表时间：
2005-04
期刊：
影响因子：
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通讯作者：
J. Minz;S. Lim;Cheng-Kok Koh
中科院分区：
文献类型：
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作者：
J. Minz;S. Lim;Cheng-Kok Koh
通过系统级封装（SOP）实现的3D封装是片上系统（SOC）的可行替代方案，可满足当今混合信号系统集成的严格要求。在这项工作中，我们提出了一个3D模块和decap（去耦电容）的布局算法，同时降低了电源噪声和线拥塞。我们为3D电源噪声和拥塞分析提供高效算法，以指导我们的3D模块布局过程。此外，我们在需要开盖的模块周围分配白色空间，以抑制电源噪声，同时最大限度地减少面积开销。在我们的实验中，我们实现了开盖量和拥塞的改善，只有小的面积，线长和运行时间的增加。
3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today's mixed signal system integration. In this work, we propose a 3D module and decap (decoupling capacitance) placement algorithm that simultaneously reduces the power supply noise and wire congestion. We provide efficient algorithms for 3D power supply noise and congestion analysis to guide our 3D module placement process. In addition, we allocate white spaces around the modules that require decaps to suppress the power supply noise while minimizing the area overhead. In our experimentation, we achieve improvements in both decap amount and congestion with only small increase in area, wirelength, and runtime.