Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology
Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology
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采用 65 nm CMOS 技术的具有自适应均衡和波特率时钟和数据恢复功能的 60 Gb/s 288 mW NRZ 收发器的设计技术
DOI：
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发表时间：
2017
影响因子：
5.4
通讯作者：
E. Alon
中科院分区：
文献类型：
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作者：
Jaeduk Han;Nicholas Sutardja;Yue Lu;E. Alon
一个完整的60 Gb/s的非归零收发器的自适应均衡以及波特率的时钟和数据恢复（CDR）的设计技术进行了演示。完整的均衡前端具有逐路径自适应和逐采样器失调校准功能，可在实际通道上实现60 Gb/s的工作速率。前端的电流积分用于节能均衡，并与积分相位抖动相结合，以实现稳健的波特率CDR。自适应误差采样器输出与相位抖动序列的相关性指示相位偏移的方向，并且与过采样CDR相比，所得到的波特率CDR通过不需要额外的时钟相位/时钟转换器而节省了功率和复杂度。建议的65纳米CMOS收发器工作在60 Gb/s的30%UI的眼开度和消耗288 mW，而在30 GHz的0.7米的Twinax电缆均衡21 dB的损失。
Design techniques for a complete 60-Gb/s non-return-to-zero transceiver with adaptive equalization as well as baud-rate clock and data recovery (CDR) are demonstrated. A complete equalization front end with per-path adaptation and per-sampler offset calibration enables 60-Gb/s operation over realistic channels. Current integration in the front end for energy-efficient equalization is combined with integration phase dithering to realize a robust baud-rate CDR. Correlation of the adaptive error sampler output with the phase dithering sequence indicates the direction of phase offset, and the resulting baud-rate CDR saves power and complexity compared to an oversampling CDR by not requiring additional clock phases/deserializers. The proposed 65-nm CMOS transceiver operates at 60 Gb/s with an eye opening of 30% UI and consumes 288 mW while equalizing 21 dB of loss at 30 GHz over a 0.7-m Twinax cable.