Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model
复制标题
可变延迟模型下组合 CMOS 电路中加权开关活动的最大化
DOI：
10.1109/edtc.1997.582422
复制
发表时间：
1997
期刊：
影响因子：
--
通讯作者：
J. Figueras
中科院分区：
文献类型：
--
作者：
S. Manich;J. Figueras
提出了一种在变延迟模型下寻找组合电路加权开关活性最大的矢量对的方法。加权开关活动最大化问题等价于变换电路上的故障测试问题。通过覆盖变换电路的选定故障集的测试向量来实现最大加权开关活动。自动测试和模式生成工具用于寻找最大化的向量对。在ISCAS-85基准电路上验证了该方案的有效性，仿真结果表明，与伪随机样本仿真相比，仿真时间缩短了一个数量级，最大加权开关活跃度的估计也得到了改善。
A methodology to find the couple of vectors maximizing the weighted switching activity in combinational CMOS circuits under variable delay model is presented. The weighted switching activity maximization problem is shown to be equivalent to a fault testing problem on a transformed circuit. A maximum weighted switching activity is achieved by test vectors covering a selected set of faults of the transformed circuit. Automatic Test and Pattern Generation tools are used to find the maximizing pair of vectors. The validity of the proposal is demonstrated on the ISCAS-85 benchmark circuits and the results show that the simulation time is reduced by an order of magnitude and the estimation of the maximum weighted switching activity is improved in comparison with pseudo-random sample simulation.