Modeling cache coherence misses on multicores
Modeling cache coherence misses on multicores
复制标题
对多核上的缓存一致性缺失进行建模
DOI：
10.1109/ispass.2014.6844465
复制
发表时间：
2014
期刊：
影响因子：
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通讯作者：
B. Jonsson
中科院分区：
文献类型：
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作者：
Xiaoyue Pan;B. Jonsson
在保持私有缓存一致性的同时，基于无效的缓存一致性协议引入了缓存一致性缺失。我们解决了在多核系统上使用基于无效的缓存一致性协议运行时，并行应用程序的私有缓存中预测缓存一致性缺失数量的问题。我们提出了三种新的性能模型（统一、分阶段和对称），用于从核间数据共享模式和单个核的数据重用模式的信息中估计一致性缺失的数量。统一模型和分阶段模型的输入是来自不同核的共享数据的写入频率和重用距离分布。此输入可以通过在单个核心上分析目标应用程序或静态分析数据访问模式来获得，并且不需要对共享数据的交错访问模式进行详细模拟。模型的输出是对目标应用的相干缺失数的估计。可以将输出与其他类型的失误数量结合起来，以估计每个核心私有缓存中的失误总数。该输出还可用于指导程序优化，以提高缓存性能。我们使用一组来自PARSEC基准测试套件的实际硬件上的基准测试来评估我们的模型。
While maintaining the coherency of private caches, invalidation-based cache coherence protocols introduce cache coherence misses. We address the problem of predicting the number of cache coherence misses in the private cache of a parallel application when running on a multicore system with an invalidation-based cache coherence protocol. We propose three new performance models (uniform, phased and symmetric) for estimating the number of coherence misses from information about inter-core data sharing patterns and the individual core's data reuse patterns. The inputs to the uniform and phased models are the write frequency and reuse distance distribution of shared data from different cores. This input can be obtained either from profiling the target application on a single core or by analyzing the data access pattern statically, and does not need a detailed simulation of the pattern of interleaving accesses to shared data. The output of the models is an estimated number of coherence misses of the target application. The output can be combined with the number of other kinds of misses to estimate the total number of misses in each core's private cache. This output can also be used to guide program optimization to improve cache performance. We evaluate our models with a set of benchmarks from the PARSEC benchmark suite on real hardware.