A crosstalk-aware timing-driven router for FPGAs
A crosstalk-aware timing-driven router for FPGAs
复制标题
用于 FPGA 的串扰感知时序驱动路由器
DOI：
10.1145/360276.360292
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发表时间：
2001
期刊：
影响因子：
--
通讯作者：
S. Wilton
中科院分区：
文献类型：
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作者：
S. Wilton
随着集成电路迁移到更先进的技术，很明显，串扰是一个重要的物理现象，必须考虑。串扰主要是ASIC、多芯片模块和定制芯片的问题，但它很快将成为FPGA的问题。在本文中，我们描述了第一个发布的串扰感知路由器的目标FPGA。我们表明，在一个有代表性的FPGA架构中实现的0.18毫米的技术，在存在串扰的平均路由延迟可以减少7.1%相比，路由器没有知识的串扰。大约一半的改进是由于更严格的延迟估计，一半是由于改进的路由算法。
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstalk has primarily been a concern for ASICs, multi-chip modules, and custom chips, however, it will soon become a concern in FPGAs. In this paper, we describe the first published crosstalk-aware router that targets FPGAs. We show that, in a representative FPGA architecture implemented in a 0.18mm technology, the average routing delay in the presence of crosstalk can be reduced by 7.1% compared to a router with no knowledge of crosstalk. About half of this improvement is due to a tighter delay estimator, and half is due to an improved routing algorithm.