Graphene field effect transistors with parylene gate dielectric
Graphene field effect transistors with parylene gate dielectric
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DOI：
10.1063/1.3273396
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发表时间：
2009-12-14
影响因子：
4
通讯作者：
Szkopek, T.
中科院分区：
文献类型：
--
作者：
Sabri, S. S.;Levesque, P. L.;Szkopek, T.
我们报道了具有聚对二甲苯背栅和暴露的石墨烯顶面的石墨烯场效应晶体管的制造和表征。在94 nm热氧化硅上的168 nm聚对二甲苯的背栅叠层允许使用光学反射显微镜来识别剥离的石墨烯薄片。在10（12）/cm（2）电子/空穴密度下，在电接触石墨烯中观察到10 000 cm（2）/Vs的室温迁移率。聚对二甲苯门控器件在环境条件下表现出稳定的中性点栅极电压，并且比在氧化硅上直接剥离的石墨烯薄片中观察到的滞后更小。
We report the fabrication and characterization of graphene field effect transistors with parylene back gate and exposed graphene top surface. A back gate stack of 168 nm parylene on 94 nm thermal silicon oxide permitted optical reflection microscopy to be used for identifying exfoliated graphene flakes. Room temperature mobilities of 10 000 cm(2)/Vs at 10(12)/cm(2) electron/hole densities were observed in electrically contacted graphene. Parylene gated devices exhibited stable neutrality point gate voltage under ambient conditions and less hysteresis than that observed in graphene flakes directly exfoliated on silicon oxide.