Implementing and evaluating stream applications on the dynamically reconfigurable processor
Implementing and evaluating stream applications on the dynamically reconfigurable processor
复制标题
在动态可重构处理器上实现和评估流应用程序
DOI：
10.1109/fccm.2004.42
复制
发表时间：
2004
期刊：
影响因子：
--
通讯作者：
T. Awashima
中科院分区：
文献类型：
--
作者：
N. Suzuki;Shunsuke Kurotaki;Masayasu Suzuki;N. Kaneko;Yutaka Yamada;Katsuaki Deguchi;Yohei Hasegawa;H. Amano;K. Anjo;M. Motomura;K. Wakabayashi;Takeo Toi;T. Awashima
动态可重构处理器（DRP）是由NEC电子公司开发的一种粗粒度可重构处理器，它从16个电路配置或上下文的片上存储库中选择数据路径，以在单个DRP芯片上实现不同的逻辑。几个流的应用程序已实施的DRP-1，第一个原型芯片，并评估结果。通过使用处理元件（PE）和分布式存储器模块计算CPU，DRP-1在一些流应用示例中优于pPENT III/4和嵌入式CPU MIPS 64。我们还提出了可重构处理器上适用的编程技术，并讨论了它们在提高系统性能的可行性。
Dynamically reconfigurable processor (DRP) developed by NEC electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the first prototype chip, and evaluation results are presented. By computing parallelly using the processing elements(PEs) and distributed memory modules, DRP-1 outperformed pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on reconfigurable processors and discuss their feasibility in boosting system performance.