Timing optimization of FPGA placements by logic replication
Timing optimization of FPGA placements by logic replication
复制标题
通过逻辑复制对 FPGA 布局进行时序优化
DOI：
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复制
发表时间：
2003
期刊：
影响因子：
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通讯作者：
J. Lillis
中科院分区：
文献类型：
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作者：
Giancarlo Beraudo;J. Lillis
逻辑复制布局级时序优化的FPGA的背景下进行了研究。我们观察到，关键路径的互连延迟占主导地位，往往是非常迂回。我们提出了一个系统的复制技术来“拉直”这样的路径。由此产生的算法有几个组成部分：单元格选择，插槽选择重复单元格，扇出分区和布局合法化。该算法的描述和有前途的初步实验结果报告与关键路径延迟的29%的改善。
Logic replication for placement level timing optimization is studied in the context of FPGAs. We make the observation that critical paths are dominated by interconnect delay and are frequently highly circuitous. We propose a systematic replication technique to "straighten" such paths. The resulting algorithm has several components: cell selection, slot selection for a duplicate cell, fanout partitioning and placement legalization. This algorithm is described and promising preliminary experimental results are reported with up to 29% improvement in critical path delay.