New Tunnel FET Charge-Trapping Memory with Large Memory Window for Ultra Low Power Operation
New Tunnel FET Charge-Trapping Memory with Large Memory Window for Ultra Low Power Operation
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新型隧道 FET 电荷捕获存储器,具有大内存窗口,可实现超低功耗运行
DOI:
10.7567/ssdm.2017.ps-4-10
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发表时间:
2017
期刊:
影响因子:
--
通讯作者:
H. Kino
中科院分区:
文献类型:
--
作者:
H. Kino
Charge-trapping memory needs a larger memory window for low power operation. Tunnel FET structure is one of the promising structure to achieve the large memory window due to its asymmetric structure. In the case of tunnel FET with N+ gate, there is higher electric field between P+ source and N+ gate edge compared with conventional FET structure. This high electric field enables a large amount of charge injection into the charge storage layer. In this study, we fabricated a SONOS memory with tunnel FET and evaluated write-operation characteristics.