Fault tolerance for multi-threaded applications by leveraging hardware transactional memory
Fault tolerance for multi-threaded applications by leveraging hardware transactional memory
复制标题
通过利用硬件事务内存实现多线程应用程序的容错
DOI：
10.1145/2482767.2482773
复制
发表时间：
2013
影响因子：
0.8
通讯作者：
A. Cristal
中科院分区：
文献类型：
--
作者：
Gulay Yalcin;O. Unsal;A. Cristal
提供容错能力，特别是为关键任务应用程序提供容错能力，以便检测瞬时和永久性故障并从中恢复，是处理器设计人员的主要需求之一。然而，由于比较指令流的结果、对整个系统设置检查点以及从检测到的错误恢复到约定的状态，多线程应用程序的容错能力会导致性能大幅下降。在本研究中，我们提出了 FaulTM-multi，这是一种针对在事务内存硬件上运行的多线程应用程序的容错方案，可减少这些性能下降。对于基于锁的并行和 TM 应用程序，FaulTM-multi 将传统故障检测方案锁步的性能下降分别从 23% 和 9% 降低到 10% 和 2%。此外，与最先进的检查点方案 Rebound 相比，FaulTM-multi 创建的检查点减少了 28%。
Providing fault tolerance especially to mission critical applications in order to detect transient and permanent faults and to recover from them is one of the main necessity for processor designers. However, fault tolerance for multi-threaded applications presents high performance degradations due to comparing the results of the instruction streams, checkpointing the entire system and recovering from the detected errors to an agreed state. In this study, we present FaulTM-multi, a fault tolerance scheme for multi threaded applications running on transactional memory hardware which reduces these performance degradations. FaulTM-multi decreases the performance degradation of lockstepping, a conventional fault detection scheme, from 23% and 9% to 10% and 2% for lock-based parallel and TM applications respectively. Also, FaulTM-multi creates 28% less checkpoints compared to Rebound, the state of the art checkpointing scheme.