On the feasibility of combining on-line-test and self repair for logic circuits
On the feasibility of combining on-line-test and self repair for logic circuits
复制标题
逻辑电路在线测试与自修复相结合的可行性探讨
DOI:
10.1109/ddecs.2013.6549814
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发表时间:
2013
期刊:
影响因子:
--
通讯作者:
H. Vierhaus
中科院分区:
文献类型:
--
作者:
T. Koal;Markus Ulbricht;P. Engelke;H. Vierhaus
Integrated circuits and systems implemented by using nano-technologies show a combination of known and new faults effects, which affect their reliability and their operational life time, specifically in safety-critical applications. Transient fault effects such as single and multiple event upsets (SEUs and MEUs) require fast error detection and compensation. Permanent faults may occur due to early life time failures on one side and stress-induced rapid aging on the other hand. They need to be compensated by repair technologies, preferably using “fresh” resources for the replacement of faulty functional units. As self repair is typically not a fast process and requires extra time while the system is off-line, on-line fault compensation must also catch and handle permanent faults that occur during “hot” operation. If on-line-test and error compensation on one side and repair technologies on the other hand are implemented independently, the resulting overhead in redundant circuitry becomes prohibitively high. In the following paper we therefore introduce a new concept of logic design which can meet the essential demands at reasonable cost using a flexible allocation of redundancy.