A High-Density 45 nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing
A High-Density 45 nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing
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DOI：
10.1109/isscc.2008.4523216
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发表时间：
2008-04
影响因子：
5.4
通讯作者：
N. Verma;A. Chandrakasan
中科院分区：
文献类型：
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作者：
N. Verma;A. Chandrakasan
高密度SRAM利用积极的小的位单元，这是极端的可变性，降低其读取SNM和读取电流。此外，阵列性能还受到灵敏放大器偏移和选通定时不确定性的限制。本文提出了一种针对所有这些性能下降的灵敏放大器：具体地说，简单的失调补偿降低了对变化的敏感性，同时对高速节点施加最小的负载;稳定的内部基准电压作为自触发再生的内部手段，以避免外部选通路径中的跟踪失配;精确的小信号检测承受小的读取电流，从而可以优化其它位单元参数;并且单端感测提供了对非对称位单元的兼容性，这可以具有改进的操作裕度。该设计与由0.25 mum 2 6 T位单元组成的64 kb高密度阵列集成。一个原型，在低功耗45纳米CMOS，比较其性能与传统的检测放大器，表现出改善4倍的访问时间西格玛和34%的整体最坏情况下的访问时间。
High-density SRAMs utilize aggressively small bit-cells, which are subject to extreme variability, degrading their read SNM and read-current. Additionally, array performance is also limited by sense-amplifier offset and strobe-timing uncertainty. This paper, presents a sense-amplifier that targets all of these performance degradations: specifically, simple offset compensation reduces sensitivity to variation while imposing minimal loading on high-speed nodes; stable internal voltage references serve as an internal means to self-trigger regeneration to avoid tracking mismatch in an external strobe-path; precise small-signal detection withstands small read-currents so that other bit-cell parameters can be optimized; and single-ended sensing provides compatibility to asymmetric bit-cells, which can have improved operating margins. The design is integrated with a 64-kb high-density array composed of 0.25 mum2 6T bit-cells. A prototype, in low-power 45 nm CMOS, compares its performance with a conventional sense-amplifier, demonstrating an improvement of 4X in access-time sigma and 34% in overall worst case access time.