A 1-V 6-b 50-MSamples/s current-interpolating CMOS ADC
A 1-V 6-b 50-MSamples/s current-interpolating CMOS ADC
复制标题
1V 6b 50MSamples/s 电流插值 CMOS ADC
DOI：
10.1109/4.839926
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发表时间：
2000
影响因子：
5.4
通讯作者：
S. Gillig
中科院分区：
文献类型：
--
作者：
B. Song;P. Rakers;S. Gillig
CMOS模数转换器（ADC）需要自举技术或低阈值器件才能在低电源电压下工作。一个6-B 50-MSamples/s的ADC在正常阈值CMOS工作时，单电池低至0.9 V，无需自举。采用电流插值方法来配置1 V ADC系统，该系统不允许供电轨之间的电压超过1 V/sub GS/+1 V/sub DSat/。该原型采用轨到轨输入，采用单个系统时钟工作。该芯片采用0.35-/spl μ/mCMOS工艺制作，面积为2.4/spl times/2 mm/sup 2/，模拟和数字电源功耗均为10 mW。
CMOS analog-to-digital converters (ADC's) require either bootstrapping techniques or low-threshold devices to function at low supply voltages. A 6-b 50-MSamples/s ADC in normal-threshold CMOS operates with a single battery cell as low as 0.9 V without bootstrapping. A current-interpolation approach is taken to configure a 1-V ADC system that does not allow more than one V/sub GS/ plus one V/sub DSsat/ between the supply rails. The prototype takes a rail-to-rail input and works with a single system clock. The chip fabricated in 0.35-/spl mu/m CMOS occupies an area of 2.4/spl times/2 mm/sup 2/ and consumes 10 mW each in analog and digital supplies.