Demonstration of an n-channel inversion mode GaAs MISFET
Demonstration of an n-channel inversion mode GaAs MISFET
复制标题
n 沟道反转模式 GaAs MISFET 演示
DOI：
10.1109/iedm.1989.74196
复制
发表时间：
1989
期刊：
影响因子：
--
通讯作者：
J. Hutchby
中科院分区：
文献类型：
--
作者：
G. Fountain;R. Rudder;S. Hattangady;R. Markunas;J. Hutchby
仅提供摘要形式。采用SiO/sub 2/（15 nm）/Si（1 nm）/GaAs复合结构，研制了一种可工作的GaAs反型n沟MISFET。这一结果是基于原位氢清洗过程（用于制备GaAs表面之前的Si-SiO/sub 2/沉积），低温赝晶Si沉积过程，和低温高品质的SiO/sub 2/沉积过程，所有顺序进行超高真空/负载锁定系统。第一工作器件在栅极长度和宽度分别为2 μ m和50 μ m时表现出0.26 mS/mm的DC击穿电压。电容-电压分析表明，带隙电子陷阱密度约为4 × 10 ~（-1）/ cm ~（-2）/. <<ETX>>
Summary form only given. An operational GaAs inversion mode n-channel MISFET has been demonstrated using a composite SiO/sub 2/ (15 nm)/Si (1 nm)/GaAs structure. This result is based on an in situ hydrogen cleaning process (used to prepare the GaAs surface just prior to the Si-SiO/sub 2/ deposition), a low-temperature pseudomorphic Si deposition process, and a low-temperature high-quality SiO/sub 2/ deposition process, all performed sequentially in an ultrahigh-vacuum/load locked system. The first working devices exhibit a DC transconductance of 0.26 mS/mm at a gate length and width of 2 mu m and 50 mu m, respectively. Capacitance-voltage analysis of MIS capacitors on chip with the transistors indicates that the midgap electron trap density is on the order of 4*10/sup 11/ cm/sup -2/.<<ETX>>