HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications
HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications
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HPAM:适用于容错应用的 8 位高性能近似乘法器设计
DOI:
10.1109/isqed54688.2022.9806220
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发表时间:
2022
期刊:
影响因子:
--
通讯作者:
D. Banerjee
中科院分区:
文献类型:
--
作者:
Divy Pandey;Vishesh Mishra;Saurabh Singh;Sagar Satapathy;Babita Jajodia;D. Banerjee
In recent times, approximate computing is widely employed in the design of power-aware hardware architectures. Approximate computing techniques can be used to benefit a major class of error-resilient applications. It has emerged as a computing paradigm that can efficiently cater several popular applications that can tolerate bounded imprecision in results. Applications such as image processing, machine learning, and deep learning extensively use multiplication and addition operations on 8-bit numbers. This work proposes an 8-bit High-Performance Approximate Multiplier (HPAM) for error resilient applications. HPAM is capable of providing significant speedup at application end while simultaneously maintaining high accuracy standards. It is designed the motivation of providing an broad error bound thus making it worthy in catering applications with high accuracy demands as well as low accuracy standards. Additionally, an approximate version of conventional ripple carry adder (RCA), a Segmented Ripple Carry Approximate Adder (SRCA) is also proposed along with this work. To validate the efficacy of the proposed design, its performance is compared with the conventional Wallace tree multiplier and the existing state-of-the-art designs such as TOSAM, DSM, and LETAM. On average, HPAM provides a speedup of 27.08% and 48.06% more accurate results in comparison to the existing state-of-the-art designs.