Carry Propagation Free Adder/Subtracter Using Adiabatic Dynamic CMOS Logic Circuit Technology
Carry Propagation Free Adder/Subtracter Using Adiabatic Dynamic CMOS Logic Circuit Technology
复制标题
采用绝热动态 CMOS 逻辑电路技术的无进位传播加法器/减法器
DOI：
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发表时间：
2003
影响因子：
0.5
通讯作者：
Mitsuru Mizunuma
中科院分区：
文献类型：
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作者：
Yasuhiro Takahashi;K. Konta;Kazukiyo Takahashi;M. Yokoyama;K. Shouno;Mitsuru Mizunuma
本文描述了一种采用绝热动态cmos逻辑(ADCL)电路技术的无进位加减器(CPFA/S)超大规模集成电路的设计。利用PSPICE仿真器，对ADCL 1位CPFA/S和CMOS1位CPFA/S的功耗进行了比较，结果表明所提出的ADCL电路的功耗约为CMOS1位CPFA/S的1/3。比较了ADCL4位CPFA/S和ADCL4位纹波进位加减器(RCA/S)的晶体管个数、传输延迟时间和能量消耗。晶体管个数和传播延迟时间分别减少了7.02%和57.1%。同时，耗能降低了78.4%。电路运行和性能评估使用1位CPFA/S的ADCL链，该链采用1.2µMCMOS工艺制造。实验结果表明，该加减法运算的时钟频率高达1 MHz左右。此外，包括电源在内，ADCL 1位CPFA/S的总功耗为28.7µW。
SUMMARY This paper describes a design of a Carry Propagation Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1 bit CPFA/S is compared with that of the CMOS 1 bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/3 as high as that of the CMOS circuits. The transistors count, propagation-delay time and energy dissipation of the ADCL 4 bit CPFA/S are compared with those of the ADCL 4 bit Ripple Carry Adder/Subtracter (RCA/S). The transistors count and propagation-delay time are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1 bit CPFA/S fabricated in a 1.2 µm CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1 MHz. In addition, the total power dissipation of the ADCL 1 bit CPFA/S is 28.7 µW including the power supply.