Investigation of Electrostatic Gating in Two-Dimensional Transitional Metal Dichalcogenide (TMDC) Field Effect Transistors (FETs)
Investigation of Electrostatic Gating in Two-Dimensional Transitional Metal Dichalcogenide (TMDC) Field Effect Transistors (FETs)
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DOI：
10.1109/nmdc.2018.8605859
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发表时间：
2018-10
期刊：
影响因子：
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通讯作者：
Arnob Islam;Xia Liu;Bradley Odhner;M. A. Tupta;P. Feng
中科院分区：
文献类型：
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作者：
Arnob Islam;Xia Liu;Bradley Odhner;M. A. Tupta;P. Feng
在基于原子薄半导体及其异质结构的快速出现的二维（2D）电子和光电器件的积极和不断增长的探索中，更好地理解静电门控是非常重要的，特别是用于通过采用具有低亚阈值摆幅（SS）和高开关比的2D场效应晶体管（FET）来实现逻辑和开关器件。（I_{\martrm {O}\martrm {n}}/I_\text{Off}）$.在这项研究中，我们提出并证明了一种方法，包括一个组合的两个探针和四个探针的$I$-$V$测量二维过渡金属二硫属化物（TMDC）场效应管，以揭示沟道和接触电阻的演变分别，在开关状态之间切换的栅极电压的变化。在二维TMDC场效应晶体管与肖特基势垒（SB）接触，我们证明，开关状态之间的切换主要是通过调制SB由于通过静电门控电场的变化。因此，晶体管特性主要由施加栅极电压时的接触电阻变化决定。我们提出了我们的方法，二维TMDC（MoS 2，MoTe 2）场效应管。此外，我们也进行了C-V测量，以研究TMDC FET中界面陷阱态和量子电容的存在。
In the active and growing explorations of the rapidly emerging two-dimensional (2D) electronic and optoelectronic devices based upon atomically thin semiconductors and their heterostructures, developing better understanding of electrostatic gating is very important, especially for realizing logic and switching devices by employing 2D field effect transistors (FETs) with low subthreshold swing (SS) and high on-off ratio $(I_{\mathrm{O}\mathrm{n}}/I_\text{Off})$. In this study, we propose and demonstrate a method that includes a combination of two-probe and four-probe $I$-$V$ measurements on 2D transition metal dichalcogenide (TMDC) FETs to uncover the evolution of resistance of channel and contacts separately, upon change of gate voltage during switching between On and Off states. In 2D TMDC FETs with Schottky barrier (SB) contacts, we demonstrate that switching between On and Off states is primarily attained by modulating SBs due to change of electric field via electrostatic gating. Therefore, transistor characteristics is mostly determined by the contact resistance change upon the application of gate voltage. We present our method for 2D TMDC (MoS2, MoTe2) FETs. In addition, we also perform C-V measurements to investigate the presence of interface trap states and quantum capacitance in TMDC FETs.