Evolutionary Fault Tolerance Method Based on Virtual Reconfigurable Circuit With Neural Network Architecture
Evolutionary Fault Tolerance Method Based on Virtual Reconfigurable Circuit With Neural Network Architecture
复制标题
基于神经网络架构虚拟可重构电路的进化容错方法
DOI：
--
复制
发表时间：
2018
影响因子：
14.3
通讯作者：
Mengfei Yang
中科院分区：
文献类型：
--
作者：
Gong Jian;Mengfei Yang
随着计算机和电子技术的不断发展，人工智能的思想已经融入到容错研究中。演化硬件容错技术作为一种在高可靠性和高安全性应用中有价值和前景的智能容错技术，正在成为一种重要的、应用广泛的方法。然而，这种技术面临着两个难题：进化电路规模和进化效率。针对这些问题，我们提出了一种基于神经网络结构的虚拟可重构电路(NNA-VRC)可编程体系结构，并基于该可编程体系结构提出了一种进化容错方法。基于NNA-VRC的演化方法简化了可编程体系结构的结构和配置，避免了电路演化过程中的非法互连，实现了高层次(模块级)的演化。本文的实验结果表明，该方法能有效地进化出功能模块规模电路。此外，基于NNA-VRC的进化方法能够从多种注入故障模式中恢复，具有很强的容错性。
With the continuous development of computer and electronics, the idea of artificial intelligence has been integrating into the fault tolerance research. As a valuable and prospective intelligent fault tolerance technique in high reliability and high safety applications, the evolvable hardware fault tolerance technique is becoming an important and widely applicable method. However, this technique confronts two difficult problems: evolved circuit scale and evolution efficiency. Toward these problems, we present a programmable architecture called neural network architecture-based virtual reconfigurable circuit (NNA-VRC), and an evolutionary fault tolerance method based on this programmable architecture. The NNA-VRC-based evolution method simplifies the structure and configuration of programmable architecture, avoids illegal interconnections during the circuit evolution, and implements high level (module level) evolution. The experiments of this paper show that a function module scale circuit is evolved efficiently. Furthermore, NNA-VRC-based evolution method can recovery from many injected fault patterns, behaving a strong feature of fault tolerance.