A 7-transistor-per-cell, high-density analog storage array with 500µV update accuracy and greater than 60dB linearity
A 7-transistor-per-cell, high-density analog storage array with 500µV update accuracy and greater than 60dB linearity
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每单元 7 个晶体管的高密度模拟存储阵列，具有 500μV 更新精度和大于 60dB 线性度
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发表时间：
2014
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通讯作者：
S. Chakrabartty
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文献类型：
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作者：
Liang Zhou;S. Chakrabartty
虽然浮栅晶体管作为一种紧凑的模拟和神经网络参数的非易失性存储器具有吸引力，但通过数字命令和控制精确和快速地适应存储参数是一个挑战。本文提出了一种高密度模拟浮门存储器阵列的设计，该阵列可以使用数字时序中断进行精确和独立的更新。该阵列的核心是我们之前报道的负反馈架构，该架构允许对FG晶体管中的冲击电离热电子注入（IHEI）过程和Fowler-Nordheim （FN）隧道过程进行线性化。使用电容开关方法，FN隧道可以独立应用于所提出的阵列的每个存储单元，而不会影响其他单元中的存储值。因此，可以实现精度大于500μV的双向数字更新，线性度大于60dB。我们使用0.5μm CMOS工艺制作的原型验证了模拟阵列的功能。
While floating-gate transistors are attractive as a compact non-volatile storage of analog and neural network parameters, precise and fast adaptation of the stored parameters through digital command and control is a challenge. In this paper we present the design of a high-density array of analog floating-gate memory that can be precisely and independently updated using digital timing interrupts. At the core of the proposed array is our previously reported negative-feedback architecture that allows linearizing of the impact ionized hot-electron injection (IHEI) process and the Fowler-Nordheim (FN) tunneling process in FG transistors. Using a capacitive switching approach, FN tunneling can be independently applied to each of memory cell of the proposed array without affecting the stored values in the other cells. As a result, bi-directional digital updates with accuracy greater than 500μV can be achieved with a linearity of more than 60dB. We have validated the functionality of the analog array using a prototype fabricated in a 0.5μm CMOS process.