Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack

Fabrication and mobility characteristics of SiGe surface channel pMOSFETs with a HfO/sub 2//TiN gate stack
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DOI:
10.1109/ted.2005.863536
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发表时间:
2006-02
影响因子:
3.1
通讯作者:
O. Weber;J. Damlencourt;F. Andrieu;F. Ducroquet;T. Ernst;J. Hartmann;A. Papon;O. Renault;B. Guillaumot;S. Deleonibus
O. Weber;J. Damlencourt;F. Andrieu;F. Ducroquet;T. Ernst;J. Hartmann;A. Papon;O. Renault;B. Guillaumot;S. Deleonibus
中科院分区:
工程技术2区
文献类型:
--
作者:
O. Weber;J. Damlencourt;F. Andrieu;F. Ducroquet;T. Ernst;J. Hartmann;A. Papon;O. Renault;B. Guillaumot;S. Deleonibus

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本文描述了TiN/HfO/sub 2//SiGe和TiN/HfO/sub 2//Si帽/SiGe栅叠层晶体管的广泛实验研究。通过对界面质量(界面状态和粗糙度)的仔细分析,我们证明了硅帽是获得高空穴迁移率增强的必要条件。基于量子力学模拟和电容-电压特性,我们表明,这种硅帽是没有贡献任何硅寄生沟道传导和退化,只有1/spl Aring/电氧化层厚度反转。由于这种界面优化,Si/sub 0.72/Ge/sub 0.28/pMOSFET在高有效场(1 MV/cm)下的迁移率比通用SiO/sub 2//Si基准高58%,比HfO/sub 2//Si基准高90%。这代表了用高spl κ//金属栅极叠层报道的在1 MV/cm下的最佳空穴迁移率结果之一。因此,我们验证了一种可能的解决方案,以大大提高空穴迁移率的Si MOSFET与高/spl kappa/栅极MOSFET。
This paper describes an extensive experimental study of TiN/HfO/sub 2//SiGe and TiN/HfO/sub 2//Si cap/SiGe gate stacked-transistors. Through a careful analysis of the interface quality (interface states and roughness), we demonstrate that an ultrathin silicon cap is mandatory to obtain high hole mobility enhancement. Based on quantum mechanical simulations and capacitance-voltage characterization, we show that this silicon cap is not contributing any silicon parasitic channel conduction and degrades by only 1 /spl Aring/ the electrical oxide thickness in inversion. Due to this interface optimization, Si/sub 0.72/Ge/sub 0.28/ pMOSFETs exhibit a 58% higher mobility at high effective field (1 MV/cm) than the universal SiO/sub 2//Si reference and a 90% higher mobility than the HfO/sub 2//Si reference. This represents one of the best hole mobility results at 1 MV/cm ever reported with a high-/spl kappa//metal gate stack. We thus validate a possible solution to drastically improve the hole mobility in Si MOSFETs with high-/spl kappa/ gate dielectrics.