Design and Analysis of an On-Chip Current-Driven CMOS Parametric Frequency Divider
Design and Analysis of an On-Chip Current-Driven CMOS Parametric Frequency Divider
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DOI：
10.1109/tcsi.2023.3249051
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发表时间：
2023-05
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通讯作者：
Mengting Yan;Hussein M. E. Hussein-Hussein-M.-E.-Hussein-144402973;C. Cassella;M. Rinaldi;M. Onabajo
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文献类型：
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作者：
Mengting Yan;Hussein M. E. Hussein-Hussein-M.-E.-Hussein-144402973;C. Cassella;M. Rinaldi;M. Onabajo
本文介绍了一种片上电流驱动CMOS参量分频器（PFD），它提供2：1分频，输出频率为2.4GHz。带有缓冲器的定制输入驱动器级可从数字时钟信号或正弦信号源生成PFD内核的输入电流，带通滤波器（BPF）级可抑制输出端的不良谐波。通过对设计考虑因素的分析和讨论，可以深入了解PFD的输入驱动条件、输出驱动器的滤波特性以及无源元件的有限质量（Q）因子和布局寄生效应的影响。一个原型芯片，在标准的65纳米CMOS工艺制造和测试。PFD驱动器所需的最低电源电压为1.4 V，输入频率为4.8 GHz，而PFD的工作频率范围为4.5 GHz至5.1 GHz，电源电压为1.5 V。据作者所知，所提出的PFD是在具有低于6GHz操作的标准CMOS工艺中的电流驱动参量分频器的第一个片上实现，这证明了片上集成到RF系统中的可行性。
This paper introduces an on-chip current-driven CMOS parametric frequency divider (PFD) that provides 2:1 frequency division with an output frequency of 2.4 GHz. A custom input driver stage with a buffer enables to generate the input current of the PFD core from a digital clock signal or sinusoidal source, and a band-pass filter (BPF) stage suppresses undesirable harmonics at the output. Analyses and discussions of design considerations provide insights into the PFD’s input driving conditions, filtering characteristics of the output driver, as well as the effects of the limited quality (Q) factor of passive components and layout parasitics. A prototype chip was fabricated in standard 65-nm CMOS technology and tested. The minimum required supply voltage for the PFD driver is 1.4 V with an input frequency of 4.8 GHz, whereas the PFD has an operating frequency range from 4.5 GHz to 5.1 GHz with a supply voltage of 1.5 V. To the best of the authors’ knowledge, the proposed PFD is the first on-chip implementation of a current-driven parametric frequency divider in a standard CMOS process with sub-6 GHz operation, which demonstrates the feasibility of on-chip integration into RF systems.