A 373 F2 2D Power-Gated EE SRAM Physically Unclonable Function With Dark-Bit Detection Technique
A 373 F2 2D Power-Gated EE SRAM Physically Unclonable Function With Dark-Bit Detection Technique
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DOI：
10.1109/asscc.2018.8579315
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发表时间：
2018-11
期刊：
影响因子：
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通讯作者：
Kunyang Liu;Y. Min;Xuan Yang;Hanfeng Sun;H. Shinohara
中科院分区：
文献类型：
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作者：
Kunyang Liu;Y. Min;Xuan Yang;Hanfeng Sun;H. Shinohara
本文提出了一种基于集成Vss偏置发生器的增强型SRAM物理不可克隆功能（PUF）。EE SRAM PUF单元将本机稳定性提高到0.21%误码率（BER）。由于环境变化或老化而可能不稳定的位单元通过轻质偏置发生器检测以确保稳定性，并且有效性通过在室温下执行的暗位检测的实验结果进行了验证。对130 nm CMOS中10个芯片的测量结果表明，在掩蔽检测到的暗位后，在0.8-1.4 V/−40−120 °C VT转角处可实现1.3×10−6 BER。纯nMOS位单元也是高度紧凑的（即，373 F2）。此外，一个2D功率门控方案实现了低操作能量，低待机功耗，和高攻击容忍度。
This paper presents an Enhancement-Enhancement (EE) SRAM physically unclonable function (PUF) with a dark-bit detection technique based on an integrated Vss-bias generator. The EE SRAM PUF cell improves native stability to 0.21% bit-error rate (BER). Bit cells that are potentially unstable due to environmental variations or aging are detected via the lightweight bias generator to ensure stability, and the effectiveness is verified with experimental results of dark-bit detection performed at room temperature. Measurement results of 10 chips in 130-nm CMOS show that after masking the detected dark bits, 1.3×10−6 BER is achieved across 0.8–1.4 V/−40−120 °C VT corners. The nMOS-only bit cell is also highly compact (i.e., 373 F2). Moreover, a 2D power-gating scheme is implemented for low operation energy, low standby power, and high attack tolerance.