An in-plane high-sensitivity, low-noise micro-g silicon accelerometer with CMOS readout circuitry
An in-plane high-sensitivity, low-noise micro-g silicon accelerometer with CMOS readout circuitry
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DOI：
10.1109/memsys.2003.1189787
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发表时间：
2003-04
影响因子：
2.7
通讯作者：
Junseok Chae;H. Kulah;Khalil Najafi
中科院分区：
文献类型：
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作者：
Junseok Chae;H. Kulah;Khalil Najafi
报道了一种高灵敏度、低噪声的平面内（横向）电容式硅微加速度计。加速度计采用0.5 mm厚，2.4/spl倍/1.0 mm/sup /证明质量和高纵横比垂直多晶硅传感电极，采用沟槽填充工艺制造。电极通过牺牲氧化层形成的1.1-/spl mu/m传感间隙与证明质量分开。测量到的器件灵敏度为5.6 pF/g。CMOS读出电路采用开关电容前端/spl Sigma/-/spl Delta/调制器，工作频率为1mhz，具有斩波稳定和相关双采样技术，可在1hz BW下，在120db动态范围内解析10af的电容。测量到加速度计- cmos接口电路的输入参考本底噪声在大气中为1.6/spl μ /g//spl径向/Hz。
A high-sensitivity, low-noise in-plane (lateral) capacitive silicon microaccelerometer utilizing a combined surface and bulk micromachining technology is reported. The accelerometer utilizes a 0.5-mm-thick, 2.4/spl times/1.0 mm/sup 2/ proof-mass and high aspect-ratio vertical polysilicon sensing electrodes fabricated using a trench refill process. The electrodes are separated from the proof-mass by a 1.1-/spl mu/m sensing gap formed using a sacrificial oxide layer. The measured device sensitivity is 5.6 pF/g. A CMOS readout circuit utilizing a switched-capacitor front-end /spl Sigma/-/spl Delta/ modulator operating at 1 MHz with chopper stabilization and correlated double sampling technique, can resolve a capacitance of 10 aF over a dynamic range of 120 dB in a 1 Hz BW. The measured input referred noise floor of the accelerometer-CMOS interface circuit is 1.6/spl mu/g//spl radic/Hz in atmosphere.