APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis
APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis
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DOI：
10.1145/3582016.3582070
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发表时间：
2023-03
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通讯作者：
J. Melchert;Kathleen Feng;Caleb Donovick;Ross G. Daly;Ritvik Sharma;Clark W. Barrett;M. Horowitz;P. Hanrahan;Priyanka Raina
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作者：
J. Melchert;Kathleen Feng;Caleb Donovick;Ross G. Daly;Ritvik Sharma;Clark W. Barrett;M. Horowitz;P. Hanrahan;Priyanka Raina
粗粒的可重新配置阵列（CGRA）处理元件（PE）的结构对CGRA上运行的应用程序的性能和能量效率有重大影响。本文介绍了Apex，这是一种为应用程序或应用程序域生成专门的PE架构的自动化方法。 Apex首先使用频繁的子图挖掘来分析应用域基准测试，以提取常见的计算子图。然后，Apex通过使用Datapath图合并算法合并子图来生成专业PES。合并的DataPath图被转换为PE规范，我们从中自动在Verilog中自动生成PE硬件说明以及将应用程序映射到PE的编译器。 PE硬件和编译器被插入灵活的CGRA生成和编译工具链中，该工具链允许对CGRA进行敏捷评估。我们评估了两个域的顶点，即机器学习和图像处理。对于图像处理应用，与通用CGRA相比，我们的具有专业PES的自动生成的CGRA的面积从5％到30％，能量减少22％至46％。对于机器学习应用，我们自动生成的CGRA的能量减少了16％至59％，而面积比通用CGRA少22％至39％。这项工作为创建应用程序域驱动的设计空间探索框架铺平了道路，该框架自动生成有效的可编程加速器，并为硬件和编译器生成而设计的设计较低。
The architecture of a coarse-grained reconfigurable array (CGRA) processing element (PE) has a significant effect on the performance and energy-efficiency of an application running on the CGRA. This paper presents APEX, an automated approach for generating specialized PE architectures for an application or an application domain. APEX first analyzes application domain benchmarks using frequent subgraph mining to extract commonly occurring computational subgraphs. APEX then generates specialized PEs by merging subgraphs using a datapath graph merging algorithm. The merged datapath graphs are translated into a PE specification from which we automatically generate the PE hardware description in Verilog along with a compiler that maps applications to the PE. The PE hardware and compiler are inserted into a flexible CGRA generation and compilation toolchain that allows for agile evaluation of CGRAs. We evaluate APEX for two domains, machine learning and image processing. For image processing applications, our automatically generated CGRAs with specialized PEs achieve from 5% to 30% less area and from 22% to 46% less energy compared to a general-purpose CGRA. For machine learning applications, our automatically generated CGRAs consume 16% to 59% less energy and 22% to 39% less area than a general-purpose CGRA. This work paves the way for creation of application domain-driven design-space exploration frameworks that automatically generate efficient programmable accelerators, with a much lower design effort for both hardware and compiler generation.