On the design of a fourth-order continuous-time LC delta-sigma modulator for UHF A/D conversion
On the design of a fourth-order continuous-time LC delta-sigma modulator for UHF A/D conversion
复制标题
用于UHF A/D转换的四阶连续时间LC delta-sigma调制器的设计
DOI：
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发表时间：
2000
期刊：
影响因子：
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通讯作者：
Weinan Gao
中科院分区：
文献类型：
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作者：
J. A. Cherry;W. Snelgrove;Weinan Gao
我们设计和测试了一个四阶带通Delta-Sigma调制器(/SPL Delta//SPL Sigma/M)，用于将UHF模拟信号转换到数字域进行外差处理。本文第二部分设计的0.5/splµ/m SiGe调制器样机，在1 GHz的20 MHz带宽内实现了40d B的动态范围，在5 V单电源下的功耗为450 mW。在设计该调制器时，还没有建立达到某一调制器性能水平的显式设计程序。因此，本文的第一部分致力于解释选择千兆赫兹时钟跨导体/基于LC/SPL Delta//SPL Sigma/M的参数所涉及的权衡，并制定这样一个明确的设计程序。最后，我们阐述了进一步的设计考虑，对原型进行了重新设计以提高其模拟性能，并讨论了高速连续时间/SPL Delta//SPL Sigma/M对超高频模数转换的普遍适用性。
We consider the design and test of a fourth-order bandpass delta-sigma modulator (/spl Delta//spl Sigma/M) for conversion of UHF analog signals to the digital domain for heterodyning and processing there. A prototype modulator in 0.5-/spl mu/m SiGe presented in the second part of the paper achieved 40 dB of dynamic range in a 20-MHz bandwidth centered at 1 GHz and consumed 450 mW from a single 5-V supply. At the time this modulator was designed, no explicit design procedure to achieve a certain modulator performance level had been established. The first part of this paper, therefore, is devoted to explaining the tradeoffs involved in choosing the parameters for a gigahertz-clocking transconductor/LC-based /spl Delta//spl Sigma/M and formulating such an explicit design procedure. Finally, we elucidate some further design considerations, redesign the prototype to improve its simulated performance, and discuss the general appropriateness of high-speed continuous-time /spl Delta//spl Sigma/M for UHF analog-to-digital conversion.