Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic
Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic
复制标题
用于节能绝热逻辑的同步 4 相谐振电源时钟电源
DOI：
--
复制
发表时间：
2017
期刊：
影响因子：
--
通讯作者：
A. Todri
中科院分区：
文献类型：
--
作者：
Nicolas Jeanniot;G. Pillonnet;P. Nouet;N. Azémard;A. Todri
绝热逻辑是一种通过使用交流电源代替直流电源来降低数字核功耗的替代架构设计风格。数字门的节能与绝热交流电源的效率密切相关。在本文中，我们提出了一个谐振可逆电源时钟电源设计与四个不同的阶段。由于12个控制信号（每个电源3个控制信号），四个电源之间的谐振偏差得以同步。我们推导了一个4级PFAL流水线电路的能量耗散，该电路的能量耗散比非绝热CMOS流水线电路的能量耗散低2.9倍。
Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the four power-clock supplies is synchronized thanks to 12 control signals (3 controls signals per power-clock supply).We derive the energy dissipation of a 4-stage PFAL pipeline circuit supplied with the proposed resonant powerclock supply, which can dissipate up to 2.9 times less energy than a non-adiabatic CMOS pipeline.