AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs
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DOI：
10.1145/3373087.3375306
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发表时间：
2020-01
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通讯作者：
Pengfei Xu;Xiaofan Zhang;Cong Hao;Yang Zhao;Yongan Zhang;Yue Wang;Chaojian Li;Zetong Guan;Deming Chen;Yingyan Lin
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作者：
Pengfei Xu;Xiaofan Zhang;Cong Hao;Yang Zhao;Yongan Zhang;Yue Wang;Chaojian Li;Zetong Guan;Deming Chen;Yingyan Lin
深度神经网络（DNN）的最新突破推动了对特定领域硬件加速器（即，DNN芯片）。然而，设计DNN芯片是不平凡的，因为：（1）主流DNN具有数百万个参数和数十亿次操作;（2）由于对固件、处理元件、存储器层次结构等的众多设计选择，设计空间很大;以及（3）对于相同的DNN功能，存在算法/硬件协同设计需要，以具有不同的分解，这将需要不同的硬件IP，并且因此对应于显著不同的性能/能量/面积权衡。因此，DNN芯片通常需要数月至数年的时间来设计，并且需要一支由跨学科专家组成的大型团队。为了实现快速有效的DNN芯片设计，我们提出了AutoDNNchip -一种DNN芯片生成器，可以自动生成基于FPGA和ASIC的DNN芯片实现（即，具有优化的算法到硬件映射的可合成RTL代码），PyTorch）用于指定的应用程序和数据集，而无需人工参与循环。具体来说，AutoDNNchip由2个集成使能器组成：（1）Chip Predictor，它可以根据DNN模型参数、硬件配置、基于技术的IP和平台约束，准确高效地预测DNN加速器的能量、吞吐量、延迟和面积;以及（2）芯片构建器，其可以自动探索DNN芯片的设计空间（包括IP选择、块配置、资源平衡等），通过Chip Predictor优化芯片设计，然后生成可合成的RTL代码和优化的流水线，以实现目标设计指标。实验结果表明，我们的芯片预测器的预测性能与实际测量的差异<10%时，使用15 DNN模型和4个平台（边缘FPGA/TPU/GPU和ASIC）进行验证。此外，我们的AutoDNNchip生成的DNN加速器可以实现比专家制作的最先进的基于FPGA和ASIC的加速器更好的性能（高达3.86倍的改进），显示了AutoDNNchip的有效性。我们的开源代码可以在https://github.com/RICE-EIC/AutoDNNchip.git上找到。
Recent breakthroughs in Deep Neural Networks (DNNs) have fueled a growing demand for domain-specific hardware accelerators (i.e., DNN chips). However, designing DNN chips is non-trivial because: (1) mainstream DNNs have millions of parameters and billions of operations; (2) the design space is large due to numerous design choices of dataflows, processing elements, memory hierarchy, etc.; and (3) there is an algorithm/hardware co-design need for the same DNN functionality to have a different decomposition that would require different hardware IPs and thus correspond to dramatically different performance/energy/area tradeoffs. Therefore, DNN chips often take months to years to design and require a large team of cross-disciplinary experts. To enable fast and effective DNN chip design, we propose AutoDNNchip - a DNN chip generator that can automatically produce both FPGA- and ASIC-based DNN chip implementation (i.e., synthesizable RTL code with optimized algorithm-to-hardware mapping) from DNNs developed by machine learning frameworks (e.g., PyTorch) for a designated application and dataset without humans in the loop. Specifically, AutoDNNchip consists of 2 integrated enablers: (1) a Chip Predictor, which can accurately and efficiently predict a DNN accelerator's energy, throughput, latency, and area based on the DNN model parameters, hardware configurations, technology-based IPs, and platform constraints; and (2) a Chip Builder, which can automatically explore the design space of DNN chips (including IP selections, block configurations, resource balancing, etc.), optimize chip designs via the Chip Predictor, and then generate synthesizable RTL code with optimized dataflows to achieve the target design metrics. Experimental results show that our Chip Predictor's predicted performance differs from real-measured ones by <10% when validated using 15 DNN models and 4 platforms (edge-FPGA/TPU/GPU and ASIC). Furthermore, DNN accelerators generated by our AutoDNNchip can achieve better (up to 3.86X improvement) performance than that of expert-crafted state-of-the-art FPGA- and ASIC-based accelerators, showing the effectiveness of AutoDNNchip. Our open-source code can be found at https://github.com/RICE-EIC/AutoDNNchip.git.