Modelling the ARMv8 architecture, operationally: concurrency and ISA
Modelling the ARMv8 architecture, operationally: concurrency and ISA
复制标题
DOI：
10.1145/2837614.2837615
复制
发表时间：
2016-01
期刊：
影响因子：
--
通讯作者：
Shaked Flur;Kathryn E. Gray;Christopher Pulte;Susmit Sarkar;A. Sezgin;Luc Maranget;Will Deacon;Peter Sewell
中科院分区：
文献类型：
--
作者：
Shaked Flur;Kathryn E. Gray;Christopher Pulte;Susmit Sarkar;A. Sezgin;Luc Maranget;Will Deacon;Peter Sewell
在本文中，我们为ARMV8多处理器体系结构的关键方面开发语义：并发模型和64位应用程序级指令集（ISA）。我们的目标是阐明在建筑上允许的行为的范围，从而支持对并发ARM软件和硬件的正式验证，分析和测试的未来工作。建立这样的模型在本质上是困难的：它涉及捕获供应商的架构意图，其方面（尤其是出于并发）以前尚未精确定义。因此，我们首先开发出具有微体系式风味的并发模型，从许多硬件实现问题中抽象出来，但仍然接近硬件设计器的直觉。这意味着可以与Arm Architects详细讨论。然后，我们开发了一个更抽象的模型，更适合用作建筑规范，我们证明了声音W.R.T.〜第一个。指令语义涉及进一步的困难，处理细节的质量以及与并发模型接口所需的细微强度信息。我们有一种新颖的ISA描述语言，具有轻巧的类型系统，让我们同时对ARM参考手动说明描述进行了相当直接的表示。我们从组合的语义中构建了一个工具，该工具使人们可以互动或详尽地探索建筑允许的行为，用于试石器测试和（小）精灵可执行文件。我们证明了工具性能所需的一些优化的正确性。我们通过与ARM员工的讨论以及与ARM硬件行为进行比较来验证模型，以进行ISA单教学测试和同时进行的石蕊测试。
In this paper we develop semantics for key aspects of the ARMv8 multiprocessor architecture: the concurrency model and much of the 64-bit application-level instruction set (ISA). Our goal is to clarify what the range of architecturally allowable behaviour is, and thereby to support future work on formal verification, analysis, and testing of concurrent ARM software and hardware. Establishing such models with high confidence is intrinsically difficult: it involves capturing the vendor's architectural intent, aspects of which (especially for concurrency) have not previously been precisely defined. We therefore first develop a concurrency model with a microarchitectural flavour, abstracting from many hardware implementation concerns but still close to hardware-designer intuition. This means it can be discussed in detail with ARM architects. We then develop a more abstract model, better suited for use as an architectural specification, which we prove sound w.r.t.~the first. The instruction semantics involves further difficulties, handling the mass of detail and the subtle intensional information required to interface to the concurrency model. We have a novel ISA description language, with a lightweight dependent type system, letting us do both with a rather direct representation of the ARM reference manual instruction descriptions. We build a tool from the combined semantics that lets one explore, either interactively or exhaustively, the full range of architecturally allowed behaviour, for litmus tests and (small) ELF executables. We prove correctness of some optimisations needed for tool performance. We validate the models by discussion with ARM staff, and by comparison against ARM hardware behaviour, for ISA single- instruction tests and concurrent litmus tests.