High-power SOI vertical DMOS transistors with lateral drain contacts: Process developments, characterization, and modeling
High-power SOI vertical DMOS transistors with lateral drain contacts: Process developments, characterization, and modeling
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具有横向漏极触点的高功率 SOI 垂直 DMOS 晶体管：工艺开发、表征和建模
DOI：
10.1109/ted.2004.825801
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发表时间：
2004
影响因子：
3.1
通讯作者：
J. Colinge
中科院分区：
文献类型：
--
作者：
K. Pinardi;U. Heinle;S. Bengtsson;J. Olsson;J. Colinge
介绍了一种与CMOS兼容的高功率垂直双扩散MOS （VDMOS）晶体管。一种新的后端沟槽形成工艺确保了无缺陷的器件层。扫描电子显微镜显微照片显示，它几乎没有缺陷。这是通过将堑壕形成步骤移动到过程的末尾来实现的。我们的电学测量表明晶体管功能齐全。电热模拟结果表明，非箝位电感开关（UIS）测试存在很大的导通寄生双极晶体管（BJT）的风险。UIS测试用于描述电力器件在无箝位电感负载条件下的性能。当存储在电感中的所有能量直接释放到器件中时，可以预期极端的工作条件。我们对所制备的SOI VDMOSFET在静态区域的测量结果与预期的自加热对饱和行为的影响非常吻合。在100/spl℃环境温度下的实验表明，击穿电压随着漏极电压的升高而降低。这表明寄生BJT已被打开。
Silicon-on-insulator (SOI) high-power vertical double-diffused MOS (VDMOS) transistors are demonstrated with a CMOS compatible fabrication process. A new backend trench formation process ensures a defect free device layer. Scanning electron microscope micrographs show that it is nearly free of defects. This has been achieved by moving the trench formation steps toward the end of the process. Our electrical measurements indicate that the transistors are fully functional. Electrothermal simulations show that unclamped inductive switching (UIS) test involves a substantial risk of turning the parasitic bipolar transistor (BJT) on. The UIS test is used to characterize the performance of power devices under unclamped inductive loading conditions. Extreme operating condition can be expected when all the energy stored in the inductor is released directly into device. Our measurements of the fabricated SOI VDMOSFET in the static region are in good agreement with the expected impact of the self-heating on the saturation behavior. The experiments at ambient temperature of 100/spl deg/C show that the break down voltage decreases as the drain voltage increases. This indicates that a parasitic BJT has been turned on.