Design and evaluation of a multiple-valued arithmetic integrated circuit based on differential logic
Design and evaluation of a multiple-valued arithmetic integrated circuit based on differential logic
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基于微分逻辑的多值运算集成电路的设计与评估
DOI：
10.1049/ip-cds:19960710
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发表时间：
1996
期刊：
影响因子：
--
通讯作者：
M. Kameyama
中科院分区：
文献类型：
--
作者：
T. Hanyu;A. Mochizuki;M. Kameyama
提出了一种用于高速算术系统的新型多值电流模式电路的设计。采用双轨互补输入的差分逻辑电路，使信号电压摆幅小，驱动电流恒定，从而降低了电路的延迟。作为算术系统的应用，在3.5 V供电电压下，基于多值电流模差分逻辑的基数-2符号数加法器（SD）的运算速度比相应的二进制CMOS实现快1.3倍。
A design of a new multiple-valued current-mode circuit for high-speed arithmetic systems is presented. The use of a differential logic circuit with dual-rail complementary inputs makes a signal-voltage swing small with a constant driving current, so that the delay of the circuit can be reduced, As an application to arithmetic systems, it is demonstrated that the operating speed of the radix-2 signed-digit (SD) adder based on multiple-valued current-mode differential logic is 1.3 times faster than that of the corresponding binary CMOS implementation at a 3.5 V supply voltage.