Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAs
Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAs
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硬件多任务处理的方法和机制：在 Xilinx FPGA 中执行和同步完全可重定位硬件任务
DOI：
10.1109/fpl.2011.60
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
I. Martinez
中科院分区：
文献类型：
--
作者：
X. Iturbe;K. Benkrid;T. Arslan;Raul Torrego;I. Martinez
本文介绍了一种新的技术，它允许实现和执行完全可重定位的硬件任务到动态可重构FPGA的细节。我们的新技术利用内部配置访问端口（ICAP）的任务间通信和同步，导致非常少的逻辑开销。这种技术的优点包括容错，因为任务可以在结构上自由地重新定位以规避损坏的资源，以及由于更好地利用逻辑结构而获得的高性能。这项工作是一个更大的努力，在我们的小组，旨在建立一个完全可操作的动态可重构计算机，这将满足高性能，容错和高层次的编程往往相互冲突的要求的一部分。
This paper presents the details of a novel technique which allows for the implementation and execution of completely relocatable hardware tasks onto dynamically reconfigurable FPGAs. Our novel technique harnesses the internal configuration access port (ICAP) for inter-task communication and synchronization, leading to very little logic overheads. The advantages of this technique include fault-tolerance, as tasks could be relocated freely on the fabric to circumvent damaged resources, and high performance, due to better exploitation of the logic fabric. The work is part of a larger effort in our group which aims to build a fully operational dynamically reconfigurable computer which would satisfy the often conflicting requirements of high performance, fault-tolerance and high level programming.