Impact of Gate/Spacer-Channel Underlap, Gate Oxide EOT, and Scaling on the Device Characteristics of a DG-RFET
Impact of Gate/Spacer-Channel Underlap, Gate Oxide EOT, and Scaling on the Device Characteristics of a DG-RFET
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DOI：
10.1109/ted.2017.2710236
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发表时间：
2017-08-01
影响因子：
3.1
通讯作者：
Dasgupta, Sudeb
中科院分区：
文献类型：
--
作者：
Bhattacharjee, Abhishek;Dasgupta, Sudeb
一个可重新配置的场效应晶体管（RFET）的能力，提供了n型和p型特性与一个单一的晶体管是一类新兴的设备，显示出巨大的希望，成为未来的纳米电子学的基石。本文首次报道了利用广泛的3-D器件模拟对改变栅极沟道和间隔沟道下重叠对这种DG-RFET器件特性的影响进行的全面调查。结果表明，通过合理设计栅沟道和间隔沟道的下重叠，可以显著提高器件的导通电流和开关电流比。此外，还发现对于固定的等效氧化物厚度，增加栅极介电常数可以改善其延迟性能。最后，我们还报道了与这种器件的缩放特性相关的结果。
A reconfigurable field-effect transistor (RFET) with the ability to provide both n- and p-type characteristics with a single transistor is among the class of those emerging devices which show great promise to become the building block of future nanoelectronics. A comprehensive investigation using extensive 3-D device simulations on the effects of varying the gate-channel and spacer-channel underlap on the device characteristics of such a DG-RFET is reported for the first time in this paper. It is demonstrated that by appropriate designing of the gate-and spacer-channel underlap, the on-current and on-off current ratio of the device can be significantly improved. Moreover, it is also found that increasing the gate dielectric constant for a fixed equivalent oxide thickness improves its delay performance. Finally, we have also reported results related to the scaling properties of such a device.