High Density Double and Triple Layer Tantalum Pentoxide Decoupling Capacitors
High Density Double and Triple Layer Tantalum Pentoxide Decoupling Capacitors
复制标题
高密度双层和三层五氧化二钽去耦电容器
DOI：
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发表时间：
2007
影响因子：
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通讯作者：
C. Thomason
中科院分区：
文献类型：
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作者：
L. Schaper;C. Thomason
高性能集成电路（IC）需要极低阻抗的功率分配。这些器件的低电压、高电流要求必须由非常靠近IC的去耦电容提供。目前，这种去耦是由具有相对较高寄生电感的分立表面贴装电容器提供的，需要许多并联器件以在高频下提供低阻抗。薄膜、大面积五氧化二钽（TaO）介质电容器具有非常低的寄生电感，但单层器件的电容密度仅限于100 nF/cm。多层薄膜电容器可以显著增加可用电容。这些多层薄膜电容器可以以多种方式制造，允许它们嵌入FR-4层之间，IC下方，甚至嵌入IC封装中。我们先前描述了在硅上制造的双层电容器的初步结果。这些器件具有两个电介质层和三个铜板。最近，我们将该技术扩展到三层电介质层，并制造出厚度为1000 μ m的器件，总电容密度为0.6F/cm。电容器是在硅晶片上通过溅射钽金属板，然后对钽层进行湿法阳极氧化来制造的。重复该过程以产生多层堆叠。然后通过连续的光刻和蚀刻步骤从顶部到底部图案化堆叠。本文将详细描述制作过程。详细的电气性能，如电容密度，漏电流，击穿电压，和阻抗的两个和三个层的设备。使用三层工艺，我们制造了包含在DARPA计划的3-D电子组件中的设备，这些设备将被描述。筛选和测试方法，以确保设备的可靠性将简要讨论。
High-performance integrated circuits (ICs) require extremely low impedance power distribution. The low voltage, high current requirements of these devices must be provided by decoupling capacitors very close to the IC. Currently this decoupling is provided by discrete surface mount capacitors with relatively high parasitic inductance, requiring many devices in parallel to provide low impedance at high frequencies. Thin film, large area tantalum pentoxide (TaO) dielectric capacitors exhibit very low parasitic inductance, but have been limited in capacitance density to 100nF/cm for single layer devices. Multilayer thin film capacitors can substantially increase the available capacitance. These multilayer thin film capacitors can be fabricated in a variety of ways, allowing them to be embedded between FR-4 layers, under ICs, or even embedded in IC packages. We previously described the initial results of two-layer capacitors fabricated on silicon . These devices had two dielectric layers and three copper plates. Recently we extended the technology to three dielectric layers, and fabricated devices with dielectrics as thin as 1000, to yield a total capacitance density of 0.6F/cm. Capacitors were fabricated on silicon wafers by sputtering a metal plate topped with tantalum, and then wet anodizing the tantalum layer. The process was repeated to create a multilayer stack. The stack was then patterned from top to bottom by successive lithographic and etching steps. This paper will describe the fabrication process in detail. Detailed electrical properties for the resulting two and three layer devices, such as capacitance density, leakage current, breakdown voltage, and impedance will be presented. Using the three-layer process, we fabricated devices for inclusion in a 3-D electronic assembly for a DARPA program, and these devices will be described. Screening and test methods to ensure device reliability will be briefly discussed.